This application describes the architecture of a microprocessor designed for high speed data reduction and more specifically describes a microprocessor where all major data-processing circuits are connected in parallel between the input and output busses, which contain control circuitry capable of controlling all of the data-processing circuits concurrently, and which contains a modulo addressing circuit for increasing the speed with which digital data words may be accessed from previously defined circular data word lists.
There is a continuing search for means for increasing the data processing speed of computers. The use of LSI components has increased processor speed since these components are smaller and have less capacitance, thereby decreasing travel time delays.
Other general methods of increasing data reduction speed are to design special purpose computer architectures incorporating additional hardware designed for a specific end use, or to rearrange the typical general purpose computer components to provide greater speed for particular applications.
A useful configuration would be a computer optimized for the digital filtering of data based on software containing a recursive algorithm, for the high speed execution of any program which requires the repeated use of prior data words received in a data stream to solve any kind of mathematical series computation, or for accessing any word in a finite circular list of words constructed from the input data stream on a first-in first-out (FIFO) basis.